The present invention relates to the art of electronic packaging, and more specifically to assemblies incorporating semiconductor chips and to methods of making such assemblies.
Modern electronic devices utilize semiconductor chips, commonly referred to as "integrated circuits" which incorporate numerous electronic elements. These chips are mounted on substrates which physically support the chips and electrically interconnect each chip with other elements of the circuit. The substrate may be a part of a discrete chip package used to hold a single chip and equipped with terminals for interconnection to external circuit elements. Such substrates may be secured to an external circuit board or chassis. Alternatively, in a so-called "hybrid circuit" one or more chips are mounted directly to a substrate forming a circuit panel arranged to interconnect the chips and the other circuit elements mounted to the substrate. In either case, the chip must be securely held on the substrate and must be provided with reliable electrical interconnection to the substrate. The interconnection between the chip itself and its supporting substrate is commonly referred to as "first level" assembly or chip interconnection, as distinguished from the interconnection between the substrate and the larger elements of the circuit, commonly referred to as a "second level" interconnection.
The structures utilized to provide the first level connection between the chip and the substrate must accommodate all of the required electrical interconnections to the chip. The number of connections to external circuit elements, commonly referred to as "input-output" or "I/O" connections, is determined by the structure and function of the chip. Advanced chips capable of performing numerous functions may require substantial numbers of I/O connections.
The size of the chip and substrate assembly is a major concern. The size of each such assembly influences the size of the overall electronic device. Moreover, the size of each assembly controls the required distance between each chip and other chips, or between each chip or other elements of the circuit. Delays in transmission of electrical signals between chips are directly related to these distances. These delays limite the speec of operation of the device. For example, in a computer where a central processing unit operates cyclically, signals must be interchanged between the central processing unit chip and other chips during each cycle. The transmission delays inherent in such interchanges often limit the cycling rate of the central processing chip. Thus, more compact interconnection assemblies, with smaller distances between chips and smaller signal transmission delays can permit faster operation of the central processing chip.
The first level interconnection structures connecting a chip to a substrate ordinarily are subject to substantial strain caused by thermal cycling as temperatures within the device change during operation. The electrical power dissipated within the chip tends to heat the chip and substrate, so that the temperatures of the chip and substrate rise each time the device is turned on and fall each time the device is turned off. As the chip and the substrate ordinarily are formed from different materials having different coefficients of thermal expansion, the chip and substrate ordinarily expand and contract by different amounts. This causes the electrical contacts on the chip to move relative to the electrical contact pads on the substrate as the temperature of the chip and substrate changes. This relative movement deforms the electrical interconnections between the chip and substrate and places them under mechanical stress. These stresses are applied repeatedly with repeated operation of the device, and can cause breakage of the electrical interconnections. Thermal cycling stresses may occur even where the chip and substrate are formed from like materials having similar coefficients of thermal expansion, because the temperature of the chip may increase more rapidly than the temperature of the substrate when power is first applied to the chip.
The cost of the chip and substrate assembly is also a major concern. All these concerns, taken together, present a formidable engineering challenge. Various attempts have been made heretofore to provide primary interconnection structures and methods to meet these concerns, but none of these is truly satisfactory in every respect. At present, the most widely utilized primary interconnection methods are wire bonding, tape automated bonding or "TAB" and flip-chip bonding.
In wire bonding, the substrate has a top surface with a plurality of electrically conductive contact pads or lands disposed in a ring-like pattern, The chip is secured to the top surface of the substrate at the center of the ring-like pattern, so that the chip is surrounded by the contact pads on the substrate. The chip is mounted in a face-up disposition, with the back surface of the chip confronting the top surface of the substrate and with the front surface of the chip facing upwardly, away from the substrate, so that electrical contacts on the front surface are exposed. Fine wires are connected between the contacts on the front face of the chip and the contact pads on the top surface of the substrate. These wires extend outwardly from the chip to the surrounding contact pads on the substrate.
Wire bonding ordinarily can only be employed with contacts at the periphery of the chip. It is difficult or impossible to make connections with contacts at the center of the front surface of the chip using the wire bonding approach. In conventional wire bonded assemblies, the area of the substrate occupied by the chip, the wires and the contact pads of the substrate is substantially greater than the surface area of the chip itself.
In tape automated bonding, a polymer tape is provided with thin layers of metallic material forming conductors on a first surface of the tape. These conductors are arranged generally in a ring-like pattern and extend generally radially, towards and away from the center of the ring-like pattern. The chip is placed on the tape in a face down arrangement, with contacts on the front surface of the chip confronting the conductors on the first surface of the tape. The contacts on the chip are bonded to the conductors on the tape. Ordinarily, numerous patterns of conductors are arranged along the length of the tape and one chip is bonded to each of these individual patterns, so that the chips, once bonded to the tape, can be advanced through successive work stations by advancing the tape. After each chip is bonded to the metallic conductors constituting one pattern, the chip and the immediately adjacent portions of the pattern are encapsulated and the outermost portions of the metallic conductors are secured to additional leads and to the ultimate substrate. Tape automated bonding can provide the assembly with good resistance to thermal stresses, because the thin metallic leads on the tape surface are quite flexible, and will bend readily upon expansion of the chip without imposing significant stresses at the juncture between the lead and the contact on the chip. However, because the leads utilized in tape automated bonding extend outwardly in a radial, "fan out" pattern from the chip, the assembly is much larger than the chip itself.
In flip-chip bonding, contacts on the front surface of the chip are provided with bumps of solder. The substrate has contact pads arranged in an array corresponding to the array of contacts on the chip. The chip, with the solder bumps, is inverted so that its front surface faces toward the top surface of the substrate, with each contact and solder bump on the chip being positioned on the appropriate contact pad of the substrate. The assembly is then heated so as to liquify the solder and bond each contact on the chip to the confronting contact pad of the substrate. Because the flip-chip arrangement does not require leads arranged in a fan-out pattern, it provides a compact assembly. The area of the substrate occupied by the contact pads is approximately the same size as the chip itself. Moreover, the flip-chip bonding approach is not limited to contacts on the periphery of the chip. Rather, the contacts on the chip may be arranged in a so-called "area array" covering substantially the entire front face of the chip. Flip-chip bonding therefore is well suited to use with chips having large numbers of I/O contacts. However, assemblies made by flip-chip bonding are quite susceptible to thermal stresses. The solder interconnections are relatively inflexible, and may be subjected to very high stress upon differential expansion of the chip and substrate. These difficulties are particularly pronounced with relatively large chips. Moreover, it is difficult to test and operate or "burn-in" chips having an area array of contacts before attaching the chip to the substrate. Additionally, flip-chip bonding ordinarily requires that the contacts on the chip be arranged in an area array to provide adequate spacing for the solder bumps. Flip-chip bonding normally cannot be applied to chips originally designed for wire bonding or tape automated bonding, and having rows of closely spaced contacts on the periphery of the chip.
Our own prior U.S. patent application Ser. No. 07/586,758 discloses improvements in semiconductor chip assemblies and methods of making the same. As more fully set forth in the '758 application, a semiconductor chip can be connected to a substrate using a sheet-like, and preferably flexible, interposer. The interposer overlies the top, contact-bearing surface of the chip. A first surface of the interposer faces towards the chip whereas a second surface faces away from the chip. Electrical terminals are provided on the second surface of the interposer, and the interposer is also provided with apertures extending through it. Flexible leads extend through these apertures between contacts on the chip and the terminals on the second surface of the interposer. The terminals can be bonded to a substrate. Because the terminals are movable relative to the contacts on the chip, the arrangements described in the '758 application provide excellent resistance to thermal cycling. The interposer disclosed in the '758 application may include a soft, compliant layer disposed between the terminals and the chip. Because the terminals can be disposed in the area of the interposer overlying the contact pattern area of the chip, the structures described in the '758 application provide extraordinarily compact assemblies, substantially as compact as those achieved by flip-chip bonding. The invention described in the '758 application can be used with substantially any chip configuration, including so-called peripheral contact chips having contacts arranged in rows adjacent the periphery of the chip, as well as so-called area array chips having contacts disposed in an array substantially covering the entire face of the chip.
Our earlier filed U.S. patent application Ser. No. 07/673,020 discloses further improvements. The '020 application discloses enhanced forms of interposers which are arranged to be positioned on the top or front surface, i.e., the contact bearing surface of the chip and which can be disposed between the chip and a substrate. Certain interposers disclosed in the '020 application are particularly well suited for use with chips having peripheral contacts. The '020 application also discloses certain chip assemblies incorporating sheet-like interposer structures referred to as "backing elements". The backing element is adapted to underlie the bottom or rear surface of a chip. Terminals on the backing element face downwardly, away from the chip. These terminals are connected by leads to contacts on the front or top surface of the chip. However, there are still further needs for improvements in semiconductor chip assemblies and in the methods utilized to make the same.